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About Us

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

OpenHW Group Board of Directors

Miquel Moreto

- Board Member

Miquel Moreto is an Associate Professor at the Computer Architecture Departament (DAC) of the Universitat Politècnica de Catalunya (UPC), and he leads the High Performance Domain Specific Architectures team at the Barcelona Supercomputing Center (BSC). Miquel received the PhD from UPC in 2010. After finishing the PhD, he spent 15 months at the International Computer Science Institute (ICSI), affiliated with UC Berkeley, as a Fulbright Postdoctoral Research Fellowship Holder during 2011 and 2012. In 2013, he returned to Barcelona to work on multiple European projects (RoMoL, Mont-Blanc, EPI, DeepHealth, eProcessor) and industrial projects (Arm, IBM, Lenovo). Miquel has published over 125-refereed conference and journal papers and co-advised 12 PhD students. In 2019, he led the design and fabrication of Lagarto, the first academic processor developed in Spain based on the open source RISC-V instruction set architecture. Finally, he coordinates the DRAC project, which is promoting the Lagarto initiative with new generations of the processor and accelerators.

 Miquel Moreto on LinkedIn

Charlie Hauck

- Treasurer

Charlie is CEO of Bluespec, Inc., a provider of high­-level tools and IP for ASIC and FPGA design. Before Bluespec, he was general manager of Faraday Technology USA, a fabless ASIC company. Charlie has over 25 years of experience in marketing and developing RISC processors at Lexra, LSI Logic, Kendall Square Research and Commodore. Charlie received a Bachelor of Science from Johns Hopkins University and a Master of Science from the Massachusetts Institute of Technology.

 Charlie Hauck on LinkedIn

Fabien Clermidy

- Board Member

Fabien Clermidy is currently heading the digital architecture and IC design department in the research technology division of CEA. In this position, he develops the hardware and software computing strategy for High-Performance Computing, Artificial Intelligence, Cybersecurity and Cyber-Physical-Systems in relation with system developments in automotive, factory of future, avionics or defense and new nanotechnologies such as 3D chip-stacking, embedded Non-Volatile-Memories, photonic and quantum computing. Fabien has been working in CEA since 2000, holding different positions as project leader and manager of different teams. He is also a senior expert with a Ph’D supervisor degree and has published more than 80 papers in the greatest conferences such as ISSCC or DAC.

 Fabien Clermidy on LinkedIn

Liang Peng

- Board Member

Liang Peng is Vice President, head of IC-Lab and head of HMS Ecosystem Development in Futurewei Technologies. In this role, Liang leads R&D, ecosystem development in IC design, and HMS ecosystem development. He has a professional career in the semiconductor industry for 20+ years in many Silicon Valley companies including Nvidia, Intel, Rambus. He has played leading roles in technology and product development as well as strategy planning and partnership from mobile to cloud at chip and system level on GPU, CPU, video processor, memory and SOC etc. His early pioneer work and invention at Nvidia on pixel shader architecture is an industry milestone for GPU, setting the foundation for programmable shading, massive parallel computing as well as convolutional neural network for deep learning with GPU. He is also advisor and former Chairman and President of CASPA (2012-13). Liang has a B.S. in Astrophysics from Peking University, and a Ph.D. in Electrical Engineering from Cornell University.

 Liang Peng on LinkedIn

Daniel Cooley

- Board Member

Daniel Cooley serves as Silicon Labs’ Chief Technology Officer, where he is responsible for the company’s overall research and development strategy and execution. Cooley is a respected IoT industry visionary and has been instrumental in building the unmatched breadth and depth of the company’s wireless connectivity portfolio. Previously, Daniel served as Senior Vice President and Chief Strategy Officer, where he led Silicon Labs’ overall strategy, corporate development, M&A, emerging markets, and security. Prior to that, Daniel led Silicon Labs’ IoT business as Senior Vice President and General Manager. Since 2005, Cooley has served in a variety of engineering and business leadership positions at Silicon Labs in the US, Asia and Europe. He has an M.S. in Electrical Engineering from Stanford University and a B.S. in Electrical Engineering from The University of Texas at Austin and holds four patents in radio and low-power technology. In addition to the OpenHW Group, Daniel also currently serves on the board of directors for the Thinkery, Texas 4000, and the Austin Symphony Orchestra.

 Daniel Cooley on LinkedIn

OpenHW Group Executive Staff

Florian 'Flo' Wohlrab


Flo serves as CEO of the OpenHW Group a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate on open source cores, related IP, tools and software projects. His primary mission is to accelerate the adoption of high-quality, open-source RISC-V cores in mainstream applications while making it accessible for newcomers to join the vibrant RISC-V ecosystem. Previously, Flo played a pivotal role as head of sales for EMEA and Japan at Andes Technology. He successfully introduced RISC-V CPU IP to leading multinational corporations and pioneered its adoption in emerging sectors, including automotive, medical, and security.

 Florian 'Flo' Wohlrab on LinkedIn

Davide Schiavone

- Staff Member

Davide is the OpenHW Group Director of Engineering, Cores Task Group and is a PhD candidate (Spring 2020) at the Integrated Systems Laboratory of ETH Zurich (Zurich, Switzerland) in the Digital Systems group Parallel Ultra Low Power (PULP) Platform under the supervision of Prof. Luca Benini. His main research focus is on low-power energy-efficient computer architectures under the PULP project for smart systems and human-machine interfaces. Davide’s main contributions to the PULP project have been:

  • design of the RISC-V 32b core zero-riscy to minimize static power in always-on systems
  • maintaining and extending (bug fixes, verification, ISA extensions, PMP) of the RISC-V 32b core RI5CY to improve the quality, performance and features of the IP
  • maintaining the PULPissimo 32bit platform
  • implementing 3 PULPissimo-based SoC: 2 in GF22FDX and 1 in UMCL65

Davide holds Bachelor and Master degrees in Computer Engineering from Politecnico di Torino, Italy.

 Davide Schiavone on LinkedIn

Duncan Bees

- Staff Member

Duncan Bees is Director, Technical Programs of the OpenHW Group and the Eclipse Foundation. He manages the open-source engineering process supporting industrial-quality design and verification of the IP curated by the OpenHW Group, as well as the SW tools, FPGA, SoC implementations, and board level designs that support this ecosystem. Duncan has previously held executive roles with the Home Gateway Initiative (HGI) and the Digital Living Network Alliance (DLNA) and has contributed to many worldwide standards and technology initiatives. He managed R&D and product research for telecom, wireless and semiconductor companies. Duncan holds a bachelor’s degree in Applied Science from the University of British Columbia, a master’s degree with Honours in Electrical Engineering from McGill University, and has completed extensive study in machine learning, software, and data analytics. He is a certified Project Management Professional and Certified Scrum Master.

 Duncan Bees on LinkedIn

Florian Zaruba

- Staff Member

Florian is the OpenHW Group Director of Engineering, HW & SW Task Groups and a PhD student at the Integrated Systems Laboratory of ETH Zurich. His research interests include exploring new directions in energy-efficient high-performance computing. He is also the principle architect of CVA6 (Ariane). His experience includes a strong background in physical design with more than eight ASICs designed, manufactured and tested. Florian holds a Bachelor of Science degree from TU Wien and a master’s degree from ETH Zurich. See the following link for further information.

 Florian Zaruba on LinkedIn

Mario Rodriguez

- Staff Member

Mario is a Verification Engineer, currently part of the Verification Task Group. He has extensive technical experience in Verification, mainly working on developing UVM environments for complex designs and doing coverage explorations to target non-stimulated parts of the design or dead code. Additionally, he has worked on developing features for Golden Models to extend their functionality and mimic the design. He holds a Computer Science degree and MIRI Master's from Universitat Politecnica de Catalunya, Spain.

 Mario Rodriguez on LinkedIn

Mike Thompson

- Staff Member

Mike Thompson is the OpenHW Group Director of Engineering, Verification Task Group. He is a senior IC Functional Verification engineering manager with more than 20 years experience. Mike has led all aspects of the discipline with broad experience in simulation, emulation and prototyping plus management level experience of formal verification projects. He has both hands-on and management level experience with multiple SV/UVM projects and has developed teams driving SV/UVM for constrained-random, coverage driven verification efforts. Michael has been involved in a dozen successful tape-outs including five 100M gate-scale devices based on proprietary RISC processors which were verified using a novel random instruction generator and coverage model implemented in SV/VMM. Mike holds a Bachelor of Applied Science degree in Electrical and Electronics Engineering from the University of Regina, Canada.

 Mike Thompson on LinkedIn

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