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OpenHW TV Episode 2 register now - The CORE-V family of RISC-V cores

The next episode of OpenHW TV will stream live on Thursday 16th July at 11am EST / 8am PST / 4pm BST. REGISTER HERE: In this episode we look at highlights of the OpenHW Group CORE-V family of RISC-V cores, focusing on the CVE4 and CVA6 cores, an update of their current status within the OpenHW Group and how new contributors can participate in the development of these cores.

OpenHW TV Episode 1 now available on-demand

We live-streamed a world class first episode of OpenHW TV on 18th June and even exceeded our registration numbers, as guest presenters from Metrics and Imperas highlighted the open source CORE-V processor IP design verification plan. Our live Q&A session at the end with panellists from OpenHW Group including the Co-Chairs of our Verification Task Group was extremely popular and provoked some great discussion. If you missed it, you can access the entire recording here:

OpenHW Group announces OpenHW TV live online events

We’re excited to announce our latest initiative to help us amplify the value of open source processor IP – OpenHWTV. It’s a series of online events that look at the barriers to adoption of opensource IP and in each episode, we delve a little deeper into different areas with help from our 45+ members. In the first episode, which airs on 18th June @ 11am EST, we look at the importance of verification with guest presenters from Imperas, a leader in virtual platforms and high-performance software simulation and Metrics, the first true cloud-based platformfor ASIC and complex FPGA design verification.

OpenHW Group celebrates rapid growth to 40+ members and new open-source processor implementations less than a year after launch

Member organisation for collaboration, ecosystem development and open-source processor cores grows at pace.

OpenHW Group announces CORE-V Chassis SoC project and issues industry call for participation

CORE-V Chassis SoC to include CORE-V family of open-source RISC-V cores including a Linux capable 64-bit processor coupled with a 32-bit coprocessor.

OpenHW Group to showcase member projects based on CV32E and CV64A open source cores at the RISC-V Summit 2020

Ottawa, Canada - December 9 2019: The OpenHW Group will be participating at the 2nd annual RISC-V Summit in San Jose, 10-12 December 2020.

UltraSoC donates RISC-V trace implementation to enable true open-source development

Works through OpenHW Group to support design innovation and ensure ecosystem compatibility

OpenHW Group Summer 2019 Update

In case you missed it, we launched the OpenHW Group at the ETH Zurich WOSH / RISC-V Workshop this past June and we have a great event coming up this fall, Open Source Developer Forum (OSDForum)!

OpenHW Group Announced

OpenHW Group created and announces CORE-V family of open-source cores for use in high volume production SoCs Rick O’Connor, former Executive Director of the RISC-V Foundation, leads organization for collaboration, ecosystem development and open-source processor cores Ottawa, Canada and Zurich, Switzerland, June 6, 2019: A new not-for-profit global organization aims to boost the adoption of open-source processors by providing a platform for collaboration, creating a focal point for ecosystem development, and offering open-source IP for processor cores.