OpenHW TV Episode 2 Register Now - The CORE-v Family of RISC-v Cores
The next episode of OpenHW TV will stream live on Thursday 16th July at 11am EST / 8am PST / 4pm BST.
REGISTER HERE: https://bit.ly/2ZvxsmZ
In this episode we look at highlights of the OpenHW Group CORE-V family of RISC-V cores, focusing on the CVE4 and CVA6 cores, an update of their current status within the OpenHW Group and how new contributors can participate in the development of these cores.
Following the overview there will be a live Q&A session with our panellists from the OpenHW Group experts and members:
Arjan Bink - Chair OpenHW Group Cores Task Group and Principle Architect IoT Digital Systems at Silicon Labs
Jérôme Quevremont - Vice-Chair OpenHW Group Cores Task Group and RISC-V Open Hardware Project Leader at Thales
JeanRoch Coulon - RISC-V Hardware and Tools Architect at Invia (Thales)
Davide Schiavone - Director of Engineering (Cores Task Group) at OpenHW Group
Florian Zaruba - Director of Engineering (HW & SW Task Group) at OpenHW Group