Presentation: ‘Jump start your RISC-V project with OpenHW’
The OpenHW Group are joined by Imperas, Futurewei, Silicon Labs and EM Microelectronic.
This paper will address the verification methodology adopted by the OpenHW Verification Task Group to assure commercial standards for quality. Attendees will obtain the ability to use the OpenHW verification environment as a baseline to design and verify a custom RISCV core with their own value-add features.
What does OpenHW provide to its members that they can’t necessarily do by themselves, and are there any other member benefits that are particularly compelling? And what can we expect to look forward to seeing the organization achieve in 2021? EDACafe quizzes Rick O’Connor to find out more.
View the video
Feature in Semiconductor Engineering
Finally, a suggestion to read this article by Rob Van Blommestein at OneSpin Solutions in Semiconductor Engineering on RISC-V Becoming less Risky With The Right Verification.
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