A key feature of the free and open RISC-V ISA is extensibility with the ability to add user-defined custom accelerators and instructions. The CORE-V eXtension I/F project within the OpenHW Group aims to provide a standard reusable interface to simplify how these custom accelerators can be connected to the family of CORE-V cores.
The webinar provides an overview of the CORE-V eXtension I/F, the project structure and roadmap as well as the SW tool chain implications of custom instructions. We’ll also hear from one of the newest OpenHW Group members, Imagination Technologies and their motivations for joining the OpenHW ecosystem.
The session speakers include: Tim Whitfield and Trefor Southwell, Imagination Technologies; Jeremy Bennett, Embecosm; Davide Schiavone, OpenHW and the session will be moderated by Rick O’Connor, OpenHW.
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