Skip to main content

OpenHW Group Projects

For more information on joining an OpenHW Group project, please refer to the registration page. To view current members of the OpenHW Group, please refer to the Explore our Members page.

CORE-V-cores

System Verilog RTL source code for the CORE-V Family of RISC-V cores.

View the repository

CORE-V-docs

Design, Verification and Platform documentation for the CORE-V family of RISC-V cores.

View the repository

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

View the repository

riscv_vm

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board.

View the repository