Tuesday, Aug 15, 2023
OpenHW Group today announced that the industry’s most comprehensive Development Kit for an open-source RISC-V MCU is now available to be ordered.
Monday, May 29, 2023
We are looking for an experienced Chief Executive Officer to develop, oversee and control all strategic and business aspects of the non-profit corporation.
Monday, May 29, 2023
While UVM is the most popular verification methodology for ASIC and FPGA
development, it requires expensive SystemVerilog simulators to run. In
addition, setting up a new UVM testbench is a complex task requiring specialist
skill sets and the “time to first bug found” can be excessive.
Tuesday, Mar 7, 2023
Heading to Embedded World 2023? Stop by the OpenHW Group & Eclipse Foundation
booth Hall 4 – 554. OpenHW Group will be highlighting their CORE-V Family of
Open Source RISC-V Cores for High Volume Production SoCs.
Monday, Mar 6, 2023
Security has become a critical issue for the entire IoT supply chain in recent years, as the number of connected devices continues to grow and our reliance on them increases.
Wednesday, Nov 30, 2022
We have been striving to build a design that is portable across simulators and technology processes and we are excited to bring support for coherent, manycore OpenHW CORE-V CVA6 clusters on Intel FPGAs through an upcoming release. This bolsters our position of OpenPiton and CVA6 being an ideal platform for RISC-V software development as the broader ecosystem continues to mature.
Tuesday, Nov 22, 2022
… and even more, do you like to have HIGH-QUALITY, VERIFIED open-source HW IPs?
If the answer is YES, and you want to help us build them, this job offer is for you.
We are looking for a Hardware Verification Engineer that extends our ecosystem.
Click here for more details!
Thursday, Sep 1, 2022
Finding the path to amazing open-source innovation just got easier. That’s because Intel® Pathfinder for RISC-V has been launched, transforming the way SoC architects and system software developers define and design new products. Intel® Pathfinder allows for a variety of RISC-V cores and other IP to be instantiated on FPGAs and simulator platforms, with the ability to run industry-leading operating systems and tool chains within a unified IDE.
Tuesday, Jun 21, 2022
One of the great attributes of open-source technology for developers is the ability to mix and match building blocks from different sources but with complementary features to create new platforms with amazing capabilities. A recent example started as a collaboration between ETH Zurich, one of the top technical universities in Europe, and QuickLogic to produce an SoC test chip we called the “Arnold.”
Wednesday, Mar 30, 2022
When most people think about OpenHW Group, they probably think first about our RISC-V cores. The group name implies providing hardware designs compliant with the widely adopted free and open RISC-V instruction set architecture (ISA). But supporting an ISA requires much more than the register transfer level (RTL) code to implement the hardware.