While UVM is the most popular verification methodology for ASIC and FPGA
development, it requires expensive SystemVerilog simulators to run. In
addition, setting up a new UVM testbench is a complex task requiring specialist
skill sets and the “time to first bug found” can be excessive. It is therefore
no surprise that up to 70% of chip engineering budgets is spent on this task.
With Metrics DSim Cloud and Datum UVMx & Moore.io, this is no longer the case.
DSIM Cloud operates in the cloud, and requires no local computing hardware.
Datum UVMx & Moore.io (MIO) provide testbench code generation and a DevOps
toolchain that reduces design time-to-market by up to 30% with a
per-transaction Verification IP (VIP) pricing model.
This blog will give an overview of the use of these products to specify and
generate a UVM test bench to verify the CORE-V MCU RTL design from the OpenHW
Moore.io CLI (mio) is a Free & Open-Source (FOS) hardware DevOps toolchain that
performs IP management, automates EDA software, and much more. IP is stored and
downloaded from the Moore.io IP Catalog.
UVMx breaks down any digital design into specifications captured entirely via
spreadsheets from which all DV code is automatically generated.
Metrics DSim Cloud
DSim Cloud is the first and only cloud-native RTL Simulator. It combines the
agility of the cloud with the high performance of a SystemVerilog and VHDL
simulator, while letting you perform unlimited regression tests without
licenses or upfront fees. Key simulator features include:
Our primary verification approach is to replace the processor core with UVM
Agents that model the Instruction Fetch and Load/Store memory interfaces. As
the processor core is already fully verified, this approach allows the DV team
to focus their attention on the components of the CORE-V-MCU without the
overhead and complexity of the core itself and its associated toolchains. APB
peripherals will be explored both in sub-system and block-level environments
and testbenches. Agents for driving/monitoring IO protocols JTAG, I2C, SPI,
UART and SDIO as well as support (clock, reset, IRQ) and libraries (scoreboard)
are Datum VIP.
This yields the following system model for the MCU, from a DV standpoint:
The DV specifications must therefore cover the following:
1 Chip: cvmcu
2 Sub-Systems (with internal structure)
cvmcu_io: transport agent to drive and monitor the MCU’s IO ports for I2C,
UART, SPI, SDIO, CPI
cvmcu_cpi: drives and monitors the Camera Parallel Interface
cvmcu_event and cvmcu_dbg: monitor event and debug interfaces for
prediction and debugging
3 Blocks: tcounter, tprescaler, adv_timer
The Design Verification (DV) specifications are captured entirely with
spreadsheets using the UVMx notation (located under /docs):
The specifications from the sheet “chip@cvmcu” track closely with the block
diagram introduced in the previous section: