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OpenHW TV S03/E04

What's Behind the Infrastructure of the CORE-V Family

Apr 29, 2022

Automated code validation, continuous integration and test regression are cornerstones of OpenHW Group’s community-based engineering process to develop and verify high-quality processor cores. OpenHW Group is deploying a state-of-the-art Test Automation and Continuous Integration environment to achieve these objectives across our diverse projects, resulting in faster development cycles with increased quality. In this webinar, Florian Zaruba and Massimiliano (Max) Giacometti of the OpenHW Group staff will review OpenHW’s CI requirements and approaches.

A critical component to highlight is the robust design equivalence checking solution, which ensures that only the expected changes have been implemented at check-in points and no downstream functional bugs are introduced across logical Boolean, low power intent, and clock/reset domain contexts. David Stratman, Product Management Director at Cadence Design Systems, will discuss the Cadence Conformal suite of tools anchored by their Logical Equivalence Checking (LEC) solution.

Rick O’Connor of OpenHW Group will be moderating the discussion.

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OpenHW TV S03/E03

CORE-V Cores: Seeding the Next Generation of Innovators with Open-source RISC-V Processors

Mar 22, 2022

Open-source technologies have revolutionized industrial hardware and software development. These approaches are now bringing new energy to engineering education. Universities use open-source hardware and software to teach architectures and concepts while providing students hands-on experience with coding, design, and research.

In this webinar, we highlight the use of OpenHW Group CORE-V open-source RISC-V CPUs at leading Universities to teach CPU architecture, instruction-sets, and HW design. CORE-V platforms are used in bachelor’s level engineering coursework, at the master’s thesis level, and also in doctoral research. Students have contributed their work back to open-source projects at OpenHW Group, gaining valuable industrial experience. The PULP Training workshop developed by ETH Zurich compliments for-credit courses to help companies and universities start working with CORE-V CPUs and PULP microcontrollers.

The OpenHW TV presentation will be led by Davide Schiavone from OpenHW Group and Nils Wistoff from ETH Zurich.

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OpenHW TV S03/E02

Driving AI/ML Innovation with CORE-V, Open-Source RISC-V Based Processors

Mar 3, 2022

This episode features the artificial intelligence angle of the OpenHW Group CORE-V family. We will focus specifically on the CV32E40P RISC-V CPU. In the last decade we experienced that as technology scales, silicon devices become smarter and smarter, capable of implementing complex functions on hand-sized (or lower) objects such as: face recognition on mobile phones; wearable sport and health monitoring products; smart glasses; augmented reality headset; etc. Such features have become real not only due to silicon scaling but also thanks to innovative computer architectures and software stacks.

In this webinar we will show how custom extensions to the baseline RISC-V architecture and advanced parallel computer architectures enable edge-computing pattern recognition algorithms running at high energy efficiency on battery-powered systems. We will conclude by showing applications leveraging it as autonomous driving drones and mobile vision applications.

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OpenHW TV S03/E01

Fireside Chat with Nitin Dahad, Editor, embedded.com & Rick O'Connor, CEO, OpenHW Group

Feb 15, 2022

In this discussion, Nitin and Rick will discuss the key drivers for growth of open-source processor development, among other topics including the latest milestones and projects of the OpenHW Group. A live chat with attendees will be featured at the end of the interview.

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