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OpenHW TV S01E03

CORE V SW and HW in the FPGA environment

Aug 26, 2020

Episode 03 features our HW and SW Task Groups, as well as guest member Ashling. The Chairs of the groups talk about the work of the SW and HW Task Groups to date, including an outlook to future roadmaps. We also look in detail at the open source GNU toolchain for the CORE-V family of RISC-V cores provided by Embecosm, and Ashling presents an in-depth overview and live demonstration of the RiscFree Eclipse based IDE debug interface to the Genesys2 FPGA board. It’s an opportunity to see the complete CORE-V MCU FPGA development environment and hear the questions from the live Q&A session at the end with our panelists.

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OpenHW TV S01E02

The CORE-V family of RISC-V cores

Jul 16, 2020

Episode 2 of OpenHW TV gives an in-depth overview and progress to date of the CVE4 (previously RI5CY) and CVA6 (previously Ariane) cores with panelists from the OpenHW Group Cores Task Group answering questions in an interesting Q&A session at the end.

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OpenHW TV S01E01

Open source IP verification

Jun 18, 2020

We live-streamed a world class first episode of OpenHW TV on 18th June and even exceeded our registration numbers, as guest presenters from Metrics and Imperas highlighted the open source CORE-V processor IP design verification plan. Our live Q&A session at the end with panellists from OpenHW Group including the Co-Chairs of our Verification Task Group was extremely popular and provoked some great discussion.

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