Nov 20, 2020
Our last webinar episode of 2020 is now available to watch on-demand. Last month we looked at our progress on the RTL functional freeze milestone for the CVE4 and how we arrived there with the high-quality verification work from our members. We had a lot of questions about the Formal Verification work carried out to get us this far, so we have dedicated this episode to a deep-dive into the Formal Verification work and to hear from our partners on what it actually means. As always, the panel session will be live for a Q&A with all our speakers.
Oct 29, 2020
Back in June, the first episode of OpenHW TV looked at the CORE-V Verification Test Bench and our open-source RISC-V processor IP design verification plan. Just 4 months on and OpenHW Group is approaching the Functional RTL Freeze milestone for the CVE4. This episode looks at what the Functional RTL Freeze milestone means and how learnings from our early verification efforts have shaped our test bench progress, highlighting bugs and coverage gaps to help us deliver commercial grade, industrial quality verification work. Presenters include the Verification Task Group leadership team as well as key members of the OpenHW Group ecosystem who have collaborated to build our industry quality, coverage driven CORE-V Verification Test Bench.
Oct 5, 2020
Episode 4 discusses the OpenHW Group philosophy of learn, adopt, produce: learning about what is available in open-source ecoysystems, adopting and gaining experience on using these building blocks and deploying commercial grade open-source elements in production releases of designs. The episode includes updates from the OpenHW Group HW Task Group discussing the CORE-V MCU SoC project and features speakers from QuickLogic giving an overview of the ETH Zurich “Arnold” test chip and the path to production for the CORE-V MCU SoC, as well as Global Foundries talking about the features and benefits of 22FDX. You will also hear from the ARC Investment VC fund with insights into why there is early investment in open-source activity and as always, the popular Q&A at the end with the panel.
Aug 26, 2020
Episode 03 features our HW and SW Task Groups, as well as guest member Ashling. The Chairs of the groups talk about the work of the SW and HW Task Groups to date, including an outlook to future roadmaps. We also look in detail at the open source GNU toolchain for the CORE-V family of RISC-V cores provided by Embecosm, and Ashling presents an in-depth overview and live demonstration of the RiscFree Eclipse based IDE debug interface to the Genesys2 FPGA board. It’s an opportunity to see the complete CORE-V MCU FPGA development environment and hear the questions from the live Q&A session at the end with our panelists.
Jul 16, 2020
Episode 2 of OpenHW TV gives an in-depth overview and progress to date of the CVE4 (previously RI5CY) and CVA6 (previously Ariane) cores with panelists from the OpenHW Group Cores Task Group answering questions in an interesting Q&A session at the end.
Jun 18, 2020
We live-streamed a world class first episode of OpenHW TV on 18th June and even exceeded our registration numbers, as guest presenters from Metrics and Imperas highlighted the open source CORE-V processor IP design verification plan. Our live Q&A session at the end with panellists from OpenHW Group including the Co-Chairs of our Verification Task Group was extremely popular and provoked some great discussion.