Nov 12, 2021
As RISC-V evolves over time, the set of ISA features supported by each software ecosystem will also need to evolve over time, and new software ecosystems will be added. To manage this evolution, RISC-V is moving towards a model of regular annual delivery of a coherent set of ISA updates according to an ISA roadmap, and architecture profiles are intended to provide the natural structure for planning, packaging, and releasing these ISA updates.
In this OpenHW TV episode the general structure of RISC-V architecture profiles will be discussed. With reference to the OpenHW CORE-V cores roadmap. Speakers will explain how the CORE-V cores map to the RISC-V profiles along with a focus on the Zce upcoming RISC-V extension, that will be implemented in CV32E41P as a proof of concept project within the OpenHW ecosystem.
The session speakers include: Mark Himelstein, RISC-V International; Jerome Quevremont, Thales Group ; Tariq Kurd, Huawei and the session will be moderated by Davide Schiavone, OpenHW Group.
Oct 7, 2021
The CV32E4 family of open-source RISC-V CPUs is a set of processors that target embedded-class devices from edge-computing platforms to microcontrollers. This OpenHW Group TV episode shows the current state of projects surrounding the family of CORE-V IPs as: the CV32E40X for extending the computation capability of edge-nodes easily; the CV32E40S for secure applications; the CV32E20 for area-efficient microcontrollers; the CV32E40Pv2 project for completing the design and verification of the CV32E40P core for edge-computing platforms; and the CV32E41P for proving the newest Zfinx and Zce RISC-V ISA draft-extensions.
In particular, we will hear from Pascal Gouedo from the Dolphin Design team to discuss how the CV32E40Pv2 project is implemented and what are the strategies to complete it. Along with Tariq Kurd from Huawei who will describe why building the CV32E41P is important to rectify the Zfinx and Zce extensions.
The session speakers include: Pascal Gouedo, Dolphin Design; Tariq Kurd, Huawei; Davide Schiavone, OpenHW Group, and the session will be moderated by Rick O’Connor, OpenHW Group.
Jun 24, 2021
A key feature of the free and open RISC-V ISA is extensibility with the ability to add user-defined custom accelerators and instructions. The CORE-V eXtension I/F project within the OpenHW Group aims to provide a standard reusable interface to simplify how these custom accelerators can be connected to the family of CORE-V cores.
The webinar provides an overview of the CORE-V eXtension I/F, the project structure and roadmap as well as the SW tool chain implications of custom instructions. We’ll also hear from one of the newest OpenHW Group members, Imagination Technologies and their motivations for joining the OpenHW ecosystem.
The session speakers include: Tim Whitfield and Trefor Southwell, Imagination Technologies; Jeremy Bennett, Embecosm; Davide Schiavone, OpenHW and the session will be moderated by Rick O’Connor, OpenHW.
May 27, 2021
This OpenHW TV episode highlights the motivation behind the OpenHW continuous integration (CI) environment and the benefits it delivers to open source development.
The episode (broadcast live on May 27) dives into the importance of continuous integration, takes a closer look at the OpenHW CI environment, and examines how CI is employed specifically within the CORE-V Verification Test Bench and the CORE-V MCU projects.
Additionally, the webinar explores the OpenHW core-v-verif GitHub repository, the distributed workflow in place, as well as the branching strategy used to manage multiple CORE-V core verification projects within a single repository.
The expert panel includes Tim Saxe (QuickLogic) and Aimee Sutton (Metrics) alongside Mike Thompson and Florian Zaruba (OpenHW Group).
There is a 30 minute Q&A session moderated by Rick O’Connor, OpenHW Group President and CEO after around 30 minutes of presentations.
Apr 22, 2021
In this webinar led by Jeremy Bennett (at Embecosm), learn about projects run by our Software Task Group including the CORE-V FreeRTOS project featuring a demo from Robert Balas (ETH Zürich) and Shteryana Shopova (Embecosm). There are updates about the GCC and Clang/LLVM compiler tool chains from Philipp Krones and Jessica Mills (Embecosm) plus details on IDE projects from Ivan Kravets (PlatformIO) and Alexander Fedorov (Arsysop/Eclipse).
Mar 18, 2021
This TV episode focuses on OpenHW Accelerate, a $22.5M multi-year co-funded research program announced in March 2021. It showcases the first OpenHW Accelerate project, CORE-V VEC, which is a research effort to explore architectural optimizations for RISC-V vector processor implementations used in high-throughput multi-dimensional sensor data processing and ML acceleration at the Edge.
Feb 18, 2021
The fast-growing, open source OpenHW ecosystem is the focus of this episode of OpenHW TV. OpenHW IP adopters highlight the key drivers for their engagement in the OpenHW community. The episode also contains an extended Q&A session addressing questions such as what the sweet spot is for RISC-V cores such as CORE-V, and which RISC-V ISA extensions are most important. Watch the video of the webinar broadcast on 18 February now.
Jan 28, 2021
2021. New year, new episode of OpenHW TV. In the first episode of Season Two, we feature an interview between embedded.com editor-in-chief Nitin Dahad and OpenHW Group President and CEO Rick O’Connor. They discuss the latest milestones of the OpenHW Group, the roadmap for the organization, as well as the key issues that are driving the growth of open-source processor design and development. Plus there’s a brief bonus round-up of Season One showing the interesting range of guidance and discussion that was presented last year.