Oct 27, 2022
This OpenHW TV episode introduces the new Chair of the OpenHW Verification Task Group and the expanded charter to help support the growing RISC-V Verification Ecosystem.
The OpenHW Group welcomes Simon Davidmann of Imperas Software, a founding member of OpenHW, as the new Chair of the OpenHW Verification Task Group (VTG). As part of the CORE-V roadmap, the VTG is updating the successful CORE-VERIF framework to address both the increasing design complexity and improve the DV efficiency for the anticipated bandwidth required for all the new CORE-V cores in development.
To address the dual goals of improving and enhancing the OpenHW internal flows for the CORE-V roadmap and help lead the industry adoption of RISC-V, and the associated verification workload, the VTG has started a new methodology project. This episode highlights the new OpenHW VTG Advanced RISC-V Verification Methodology (ARVM) project and outlines the initial concepts and plans for a couple of the sub-projects:
RVM-FunctionalCoverage: developing open-source VIPs that can be used for many different core configurations/implementations
ARVM-Standards: defining and implementing evolving interface standards (such as RVVI) for test bench components to enable better test bench component reuse and potentially stimulate availability of compatible VIPs
Today’s speakers include:
Simon Davidmann, Chair of OpenHW Verification Task Group and CEO at Imperas Software
Peter Lewin, Director of CPU Ecosystems at Imagination Technologies
Rupert Baines, Chief Marketing Officer at Codasip
Hosted by Mike Thompson, Director of Engineering, Verification Task Group, at OpenHW Group
Oct 4, 2022
Did you miss out on Embedded World in Nuremburg, Germany in June? This episode of OpenHW TV will give you another chance to view OpenHW Group’s live presentation and hear all of the details on the new CORE-V MCU DevKit! OpenHW Group and its members announced one of the industry’s most comprehensive open-source RISC-V Development Kits at Embedded World 2022. The CORE-V MCU DevKit features the OpenHW CORE-V MCU, the CORE-V software developer kit (SDK) with full-featured Eclipse-integrated development environment (IDE) and an open printed circuit board (PCB) design that supports AWS via AWS IoT ExpressLink. The ground-breaking RISC-V-based CORE-V MCU DevKit enables software development for embedded, internet-of-things (IoT), and artificial intelligence (AI)-driven applications.
Join Rick O’Connor, President of OpenHW Group, and Richard Barry, Senior Principal Engineer at AWS, for a live Q&A session at the end of the webinar.
Jun 29, 2022
OpenHW Group is the leading global organization developing fully open-source and industry-ready RISC-V IP. Our membership spans the globe and has increasing membership within the Asia region. This seminar will introduce OpenHW Group and the objectives of OpenHW Group Asia, our Asia-focused working group. We will feature talks on CORE-V processor roadmaps, verification approaches, and software support for CORE-V cores. Please join us for this informative seminar!
Participants include Duncan Bees, Davide Schiavone and Mike Thompson from the OpenHW Group Staff, along with Wei Wu, IS-CAS, and Kan Shi, ICT-CAS.
Jun 9, 2022
This episode of OpenHW TV will focus on the verification of the CORE-V-MCU currently under development by the OpenHW Group. Followers of OpenHW TV may recall that the CORE-V-MCU started out its life as the Arnold device (https://bit.ly/3PrfMCb) from the PULP-Platform team at ETH Zürich. Arnold has been successfully implemented in silicon, so a reasonable question is: “Why does the CORE-V-MCU need more verification?”
The answer to this question lies in the goals of the CORE-V-MCU which are to enable rapid deployment of hardware and software development kits and to accelerate the design of commercial SoC devices based on CV32E40P.
Enabling hardware and software dev-kits calls for an accelerated development cycle that puts an SoC (ASIC) implementation of CORE-V-MCU into developers hands as soon as possible. To support this goal, a verification project that employs processor-driven testing is being used. This has enabled rapid deployment of a set of simple C test-programs called “cli-test”, running under FreeRTOS.
To support developers of commercial grade SoC devices requires the same level of verification that has previously been deployed on the CV32E40P core. The CORE-V-MCU-VERIF project aims to deploy a complete UVM verification environment that is capable of fully verifying the MCU as well as future commercial SoC devices based on CV32E4 cores.
The presentation is led by Mike Thompson, OpenHW Group Director of Engineering. Joining Mike are members of the Verification Task Group, Tim Saxe, CTO of QuickLogic David Poulin, President of Datum Technology Corporation.
Apr 29, 2022
Automated code validation, continuous integration and test regression are cornerstones of OpenHW Group’s community-based engineering process to develop and verify high-quality processor cores. OpenHW Group is deploying a state-of-the-art Test Automation and Continuous Integration environment to achieve these objectives across our diverse projects, resulting in faster development cycles with increased quality. In this webinar, Florian Zaruba and Massimiliano (Max) Giacometti of the OpenHW Group staff will review OpenHW’s CI requirements and approaches.
A critical component to highlight is the robust design equivalence checking solution, which ensures that only the expected changes have been implemented at check-in points and no downstream functional bugs are introduced across logical Boolean, low power intent, and clock/reset domain contexts. David Stratman, Product Management Director at Cadence Design Systems, will discuss the Cadence Conformal suite of tools anchored by their Logical Equivalence Checking (LEC) solution.
Rick O’Connor of OpenHW Group will be moderating the discussion.
Mar 22, 2022
Open-source technologies have revolutionized industrial hardware and software development. These approaches are now bringing new energy to engineering education. Universities use open-source hardware and software to teach architectures and concepts while providing students hands-on experience with coding, design, and research.
In this webinar, we highlight the use of OpenHW Group CORE-V open-source RISC-V CPUs at leading Universities to teach CPU architecture, instruction-sets, and HW design. CORE-V platforms are used in bachelor’s level engineering coursework, at the master’s thesis level, and also in doctoral research. Students have contributed their work back to open-source projects at OpenHW Group, gaining valuable industrial experience. The PULP Training workshop developed by ETH Zurich compliments for-credit courses to help companies and universities start working with CORE-V CPUs and PULP microcontrollers.
The OpenHW TV presentation will be led by Davide Schiavone from OpenHW Group and Nils Wistoff from ETH Zurich.
Mar 3, 2022
This episode features the artificial intelligence angle of the OpenHW Group CORE-V family. We will focus specifically on the CV32E40P RISC-V CPU. In the last decade we experienced that as technology scales, silicon devices become smarter and smarter, capable of implementing complex functions on hand-sized (or lower) objects such as: face recognition on mobile phones; wearable sport and health monitoring products; smart glasses; augmented reality headset; etc. Such features have become real not only due to silicon scaling but also thanks to innovative computer architectures and software stacks.
In this webinar we will show how custom extensions to the baseline RISC-V architecture and advanced parallel computer architectures enable edge-computing pattern recognition algorithms running at high energy efficiency on battery-powered systems. We will conclude by showing applications leveraging it as autonomous driving drones and mobile vision applications.
Feb 15, 2022
In this discussion, Nitin and Rick will discuss the key drivers for growth of open-source processor development, among other topics including the latest milestones and projects of the OpenHW Group. A live chat with attendees will be featured at the end of the interview.